A semiconductor device

专利摘要:
PURPOSE: A semiconductor device is provided to reduce fabrication cost through miniaturization, prevent a device from being broken by an L load switching and decrease a switching loss because of a fast switching operation. CONSTITUTION: A semiconductor substrate is prepared. A semiconductor layer is formed on the substrate, having a higher resistance than that of the substrate. A gate electrode(10) is formed on a gate insulation layer formed on the surface layer. A drain layer of the first conductivity type is selectively formed in the surface layer at one side of the gate electrode. A drain electrode(20) is coupled to the drain layer. A source layer of the first conductivity type is selectively formed in the semiconductor layer at the other side of the gate electrode. A source connecting portion is selectively formed in the semiconductor layer, connected to the source layer and having a lower resistance than that of the semiconductor layer. The source connecting portion does not reach a channel part between the source layer and the drain layer and the substrate. A contact connecting portion is selectively formed in the semiconductor layer, having a lower resistance than that of the semiconductor layer. The depth from the substrate to the contact connecting portion is deeper than that from the substrate to the source connecting portion. The first source electrode connects the source layer, the source connecting portion and the contact connecting portion. A bottom electrode connected to the substrate is formed on the bottom surface of the substrate.
公开号:KR20020085850A
申请号:KR1020020025290
申请日:2002-05-08
公开日:2002-11-16
发明作者:야스하라노리오；나카무라가즈토시；가와구치유스케
申请人:가부시끼가이샤 도시바；
IPC主号:

专利说明:

Semiconductor device {A SEMICONDUCTOR DEVICE}
[42] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly to power semiconductor devices.
[43] Background Art Conventionally, for example, a power source in which a DC-DC converter is incorporated is provided in electronic devices such as a personal computer (PC) and an information communication device. In recent years, electronic devices are becoming smaller and smaller, their driving voltages are lowering, and their driving currents are increasing. Accordingly, a power source capable of flowing a large current efficiently and corresponding to a high frequency is desired.
[44] In order to flow a large current at a low voltage, a lower ON resistance of a power semiconductor element used for a power supply is better. In addition, in order to cope with the high frequency, the switching of the power semiconductor element used for the power supply needs to be high speed.
[45] Moreover, conventionally, Schottky diodes are used for rectifying power sources. Recently, in order to be able to flow large currents at low voltages, power MOSFETs are used to rectify instead of Schottky diodes. Therefore, there is a need for a rectifying power MOSFET for rectifying in addition to the switching power MOSFET for switching between the input and the output of the power source. Such a power supply is generally referred to as a synchronous rectification circuit type power supply because the rectifying power MOSFET and the switching power MOSFET are synchronously switched.
[46] 24 is a circuit diagram of a DC-DC converter 2000 used for a typical synchronous rectification circuit power supply. Since the rectifying power MOSFET 2010 and the switching power MOSFET 2020 operate in synchronization, it is preferable that they can be switched at high speed together. In addition, since the rectifying power MOSFET 2010 and the switching power MOSFET 2020 carry a large current together, the lower the on-resistance, the better. Therefore, in the DC-DC converter 2000 of the synchronous rectification circuit system, improvements such as lower resistance of the on-resistance of the switching power MOSFET 2020 and the rectifying power MOSFET 2010, higher speed of switching, and the like are desired. .
[47] In some cases, an inductance 2050 may be connected between the source electrode 2031 of the switching power MOSFET 2020 and the output 2040 of the DC-DC converter. As described above, switching the power supply to which the inductance is connected from ON to OFF or from OFF to ON is generally referred to as L load switching.
[48] In the state where the switching power MOSFET 2020 is turned on, the potential difference between the drain electrode 2060 and the source electrode 2031 is close to zero. In addition, electrical energy is accumulated in the inductance 2050.
[49] On the other hand, when the switching power MOSFET 2020 is switched from ON to OFF, the connection between the drain electrode 2060 and the source electrode 2031 is cut off. In addition, since the inductance 2050 tries to maintain a current when the switching power MOSFET 2020 is on, the potential of the source electrode 2031 is lowered. As a result, the voltage of the drain electrode 2060 is substantially clamped, and the potential difference between the drain electrode 2060 and the source electrode 2031 is greater than the potential difference between the input 2070 and the output 2040 of the DC-DC converter 2000. Grows Depending on the size of the inductance, the voltage between the drain electrode 2060 and the source electrode 2031 may exceed the breakdown voltage between the drain electrode 2060 and the source electrode 2031. As a result, an avalanche current flows between the drain electrode 2060 and the source electrode 2031 due to avalanche breakdown.
[50] 25A is an enlarged cross-sectional view of a conventional switching power MOSFET 2020. The switching power MOSFET 2020 has a symmetrical structure with a dotted line in FIG. 25A. Therefore, it demonstrates focusing on the left side rather than this dotted line.
[51] The structure of the switching power MOSFET 2020 is as follows. The p ⁻ type silicon surface layer 2105 is formed on the p ⁺⁺ type silicon substrate 2100. The drain electrode 2060 is connected to the n-type drain layer 2110 formed in the silicon surface layer 2105. An n ⁺ type source layer 2140 is formed to connect to the source electrode 2030 via a channel portion 2130 formed under the gate electrode 2080 from the n type drain layer 2110. The source electrode 2030 is also connected to the p-type base layer 2150 formed around the n ⁺ type source layer 2140. Further, the p ⁺ -type connecting layer 2160 to connect the source electrode 2030 to the silicon substrate 2100 of the p ⁺⁺ type is formed. The source electrode 2031 is provided on the back surface of the silicon substrate 2100. Since the p ⁺ type connection layer 2160 reaches the silicon substrate 2100, the source electrode 2030 and the source electrode 2031 are electrically connected to each other. Therefore, a large current can flow when the channel portion 2130 is on.
[52] The channel portion 2130 is formed of a p ⁻ type silicon surface layer 2105 and a p type base layer 2150. Accordingly, the n-type drain layer 2110, the channel portion 2130 and the n ⁺ -type source layer 2140 parasiticly form an npn bipolar transistor.
[53] FIG. 25B is a circuit diagram of a parasitic npn bipolar transistor composed of an n-type drain layer 2110, a channel portion 2130, and an n ⁺ type source layer 2140. The base of this parasitic npn bipolar transistor is connected to the source electrode 2030 via the p-type base layer 2150.
[54] As described with reference to FIG. 24, there is a case where an avalanche current due to avalanche breakdown flows between the drain electrode 2060 and the source electrode 2031. The avalanche current passes through the resistance of the p-type base layer 2150 and flows to the source electrode 2031 through the p ⁺ -type connection layer 2160 and the p ^{+ +} -type semiconductor substrate 2100. When this current is large, the junction between the n ⁺ type source layer 2140 and the p type base layer 2150 is forward biased due to the voltage drop generated in the p type base layer 2150. As a result, the parasitic npn bipolar transistor shown in FIG. 25B is turned ON. When the parasitic npn bipolar transistor is ON, a larger current flows between the drain electrode 2060 and the source electrode 2031. Therefore, there arises a problem that the power MOSFET shown in Fig. 25A is destroyed (hereinafter, this phenomenon is referred to as "element destruction by L load switching").
[55] In addition, in FIG. 25A, the p ⁺ type connection layer 2160 must be diffused to reach the silicon substrate 2100. The p ⁺ type connection layer 2160 diffuses not only in the longitudinal direction but also in the transverse direction. When the p ⁺ type connection layer 2160 reaches the channel portion due to the lateral diffusion, the threshold voltage of the switching power MOSFET 2020 increases. When the threshold voltage of the switching power MOSFET 2020 rises, a delay of the switching occurs. In addition, the ON resistance of the switching power MOSFET 2020 increases.
[56] On the other hand, if the position of the p ⁺ type connecting layer 2160 is removed from the channel portion so that the p ⁺ type connecting layer 2160 does not reach the channel portion even when the p ⁺ type connecting layer 2160 diffuses in the lateral direction, the width of the switching power MOSFET 2020 becomes wider. All. When the switching power MOSFET 2020 becomes wider, the area of the DC-DC converter 2000 becomes larger. In the case where the switching power MOSFET 2020 is formed in a predetermined area, the number of unit cells or element units of the switching power MOSFET 2020 that can be formed is reduced. Therefore, since the total channel width of the switching power MOSFET 2020 within a predetermined area becomes small, the current at ON decreases. Therefore, the on resistance ON of the switching power MOSFET 2020 increases substantially.
[57] Fig. 26 is an enlarged cross-sectional view of another form of the conventional switching power MOSFET 2020. Figs. FIG. 25 shows a lateral MOSFET, while FIG. 26 shows a MOSFET 2020 'having a vertical trench gate.
[58] The MOSFET 2020 'may include an insulating film 2250 between the source layer 2220 connected to the source electrode 2210 and the drain layer 2240 connected to the drain electrode 2230, and the source layer 2220 and the drain layer 2240. A trench gate electrode 2260 buried in the middle;
[59] Since the MOSFET 2020 'efficiently uses the vertical surface of the gate electrode, the ON resistance can be lowered.
[60] On the other hand, the trench gate electrode 2260 is adjacent to the drain layer 2240 via the insulating film 2250, and the insulating film 2250 is thinner in order to reduce the ON resistance. Therefore, in the MOSFET 2020 ', the parasitic capacitance between the trench gate electrode 2260 and the drain layer 2240 increases. Due to this parasitic capacitance, the MOSFET 2020 'is slow in switching and is not suitable for high frequency switches.
[61] On the other hand, the rectifying power MOSFET 2010 also has the same problem as above.
[62] The present invention has been made to solve the conventional problems as described above, by reducing the manufacturing cost by miniaturization, it is possible to prevent device destruction due to L-load switching, easy to manufacture, fast switching speed switching loss It is an object to provide this small semiconductor device.
[1] 1 is a schematic partially enlarged plan view of a first embodiment of a semiconductor device according to the present invention;
[2] FIG. 2 is an enlarged cross-sectional view taken along line 2-2 'of FIG. 1;
[3] 3 is an enlarged cross-sectional view taken along line 3-3 'of FIG. 1;
[4] 4 is an enlarged cross-sectional view taken along line 4-4 'of FIG. 1;
[5] 5 is a schematic partially enlarged plan view of a second embodiment of a semiconductor device according to the present invention;
[6] 6 is an enlarged cross-sectional view taken along the line 6-6 'of FIG. 5;
[7] 7 is an equivalent circuit diagram showing a connection relationship between a gate electrode, a drain electrode, and a source electrode of the second embodiment;
[8] 8 is a graph showing a comparison between the breakdown voltage between the source and the drain of a contact-side semiconductor device and the breakdown voltage between the source and the drain of an element-side semiconductor device;
[9] 9 is a schematic partial enlarged cross-sectional view of a third embodiment of semiconductor device according to the present invention;
[10] 10 is a schematic partial enlarged cross-sectional view of a fourth embodiment of a semiconductor device according to the present invention;
[11] Fig. 11 is a sectional view of an element-side semiconductor device in Embodiment 5 when a metal plug is used for a contact-side connection portion.
[12] 12 is an enlarged cross-sectional view of a contact-side semiconductor device in a fifth embodiment using a metal plug for a contact-side connection portion;
[13] 13A and 13B are cross-sectional views of another embodiment of the contact-side semiconductor device in the fifth embodiment using the metal plug shown in FIG. 11 or 12;
[14] 14A and 14B are cross-sectional views of another embodiment of the element-side semiconductor device or the contact-side semiconductor device in the fifth embodiment using the metal plug shown in FIG. 11 or 12;
[15] FIG. 15 is a sectional view of a semiconductor device having a drain electrode at its back side as a sixth embodiment of the semiconductor device according to the present invention; FIG.
[16] 16 is a cross-sectional view of a semiconductor device having a drain electrode on its back side as a sixth embodiment of the semiconductor device according to the present invention;
[17] 17A and 17B are schematic partial enlarged plan views of an embodiment different from the embodiment shown in Fig. 1 or Fig. 5 of a semiconductor device according to the present invention;
[18] 18 is a cross-sectional view taken along the line CC ′ of FIG. 17;
[19] 19A and 19B are cross-sectional views taken along the line D-D 'of FIG. 17;
[20] 20 is a cross-sectional view taken along the line E-E 'of FIG. 17;
[21] 21A and 21B are enlarged cross-sectional views taken along line F-F 'of the power semiconductor device shown in FIG. 17A;
[22] 22A and 22B are enlarged cross-sectional views of the contact-side semiconductor device 322 according to the embodiment of FIG. 17A using a diffusion layer at the contact-side connection portion.
[23] FIG. 23 is a cross-sectional view taken along line E-E 'of the embodiment of FIG. 17A or 17B using a diffusion layer on a contact side connecting portion;
[24] 24 is a circuit diagram of a DC-DC converter 2000 used in a conventional typical synchronous rectification circuit power supply.
[25] 25A and 25B are an enlarged cross-sectional view and a circuit diagram of a conventional switching power MOSFET 2020,
[26] 26 is an enlarged cross-sectional view of another form of a conventional switching power MOSFET 2020;
[27] 27 is a partially enlarged plan view of a seventh embodiment of a semiconductor device according to the present invention;
[28] FIG. 28 is an enlarged plan view showing a dotted line portion W shown in the MOSFET chip of FIG. 27;
[29] 29 is a cross-sectional view of the device-side semiconductor device 252 along the line A-A in FIG. 28;
[30] 30 is a cross-sectional view of the wiring-side semiconductor device 352 along the line B-B in FIG. 28;
[31] 31 is an enlarged plan view of a semiconductor device according to the eighth embodiment;
[32] 32 is a sectional view of a wiring-side semiconductor device 354 according to the eighth embodiment;
[33] 33 is a cross sectional view of a wiring-side semiconductor device 356 according to the ninth embodiment;
[34] 34 is an enlarged plan view of a semiconductor device according to the tenth embodiment;
[35] 35 is an enlarged plan view of a semiconductor device according to an eleventh embodiment;
[36] 36 is an enlarged plan view showing an enlarged dotted line S shown in the MOSFET chip shown in FIG. 35;
[37] FIG. 37 is a cross-sectional view of the wiring-side semiconductor device 358 along line C-C in FIG. 36;
[38] FIG. 38 is a cross-sectional view of the element-side semiconductor device 260 using the metal plug 782 instead of the connection portion 780 in the element-side semiconductor device 252 shown in FIG. 29;
[39] 39 is a cross-sectional view of the wiring-side semiconductor device 360 in which the metal plug 782 is used in place of the connecting portion 780 in the wiring-side semiconductor device 352 shown in FIG.
[40] 40 is a schematic partially enlarged plan view of a semiconductor device according to a twelfth embodiment;
[41] 41 is a cross sectional view of a contact-side semiconductor device 362 in the present embodiment.
[63] The semiconductor device according to the present invention includes a semiconductor substrate, a first or second conductive semiconductor surface layer having a higher resistance than that of the semiconductor substrate, and a gate electrode formed on the gate insulating film formed on the surface of the semiconductor surface layer, A drain layer of the second conductive type selectively formed on the semiconductor surface layer on one side of the gate electrode, a drain electrode connected to the drain layer, a source layer of the second conductive type selectively formed on the semiconductor surface layer on the other side of the gate electrode, source Device-side connection portions selectively formed on the semiconductor surface layer so as not to reach the channel portion and the semiconductor substrate between the source layer and the drain layer, the resistance of the semiconductor surface layer being lower than that of the semiconductor surface layer, and the resistance to the semiconductor substrate A contact side connection portion, a source layer, and an element having a depth greater than that of the device side connection portion, and selectively formed on the semiconductor surface layer If the connecting portion and the back surface of the source electrode and the semiconductor substrate 1 for connecting the contact-side connecting portion connected with the semiconductor substrate provided with an electrode.
[64] According to another embodiment of the semiconductor device according to the present invention, a semiconductor substrate, a semiconductor surface layer of a first or second conductive type having a higher resistance than the semiconductor substrate and formed on the surface of the semiconductor substrate, and formed on the surface of the semiconductor surface layer A gate electrode formed on the gate insulating film, a second conductive type drain layer selectively formed on the semiconductor surface layer on one side of the gate electrode, a drain electrode connected to the drain layer, and the semiconductor surface layer on the other side of the gate electrode A source layer of a second conductivity type selectively formed in the semiconductor layer, the first semiconductor region of the first conductivity type selectively connected to the source layer and having a lower resistance than the semiconductor surface layer and selectively formed in the semiconductor surface layer to reach the semiconductor substrate, Is selectively formed on the semiconductor surface layer to have a lower resistance than the semiconductor surface layer and reach the semiconductor substrate; A second semiconductor region of a first conductive type having a non-adjacent source layer adjacent thereto, a short circuit electrode connected to the source layer and the first semiconductor region, and a source electrode connected to the semiconductor substrate on the rear surface of the semiconductor substrate; Between the drain electrode and the short electrode, a bipolar transistor is formed by the drain layer, the source layer, and a channel portion between the drain layer and the source layer, and from the drain electrode to the second semiconductor region. In the meantime, a diode is formed by the drain layer and the second semiconductor region, and the breakdown voltage between the drain layer and the second semiconductor region in the diode is between the drain electrode and the source electrode in the bipolar transistor. It is almost equal to or less than the internal pressure.
[65] Embodiment of the Invention
[66] EMBODIMENT OF THE INVENTION Hereinafter, embodiment which concerns on this invention is described with reference to drawings. This embodiment does not limit the present invention. In the semiconductor device according to the embodiment of the present invention described below, even if the p-type element is changed to n-type and the n-type element is changed to p-type for the conductive type of each element, The effect is not lost.
[67] The cross section of the conventional example shown in FIG. 25A corresponds to the cross section taken along the line 21-21 'in FIG. Therefore, in Fig. 25A, the cross section of the semiconductor device is shown symmetrically with respect to the drain electrode. However, in order to explain the embodiment which concerns on this invention, it demonstrates using the cross section along the 2-2 'line | wire or the cross section along the 3-3' line | wire of FIG. 1 for convenience.
[68] 1 is a schematic partially enlarged plan view of a first embodiment of a semiconductor device according to the present invention. In the semiconductor device according to the present embodiment, a plurality of gate electrodes 10 are formed substantially in parallel with each other, and the drain electrode 20 and the source electrode (between the gate electrodes 10 are substantially parallel with the gate electrode 10). 30 are alternately formed.
[69] 2 is an enlarged cross-sectional view showing a cross section taken along the line 2-2 'of FIG. 1 according to the first embodiment of the semiconductor device according to the present invention.
[70] 3 is an enlarged cross-sectional view showing a cross section taken along the line 3-3 'of FIG. 1 according to the first embodiment of the semiconductor device according to the present invention.
[71] The semiconductor device according to the present embodiment includes, for example, a p ⁺ type semiconductor substrate 40 made of silicon and a p ⁻ type semiconductor surface layer 50 formed on the semiconductor substrate 40 with higher resistance than the semiconductor substrate 40. And an n-type drain layer 70 formed selectively on the gate electrode 10 formed on the gate insulating film 60 formed on the surface of the semiconductor surface layer 50, and on the semiconductor surface layer 50 on one side of the gate electrode 10. ), The n ⁺ type source layer 80 and the source layer 80 selectively formed on the semiconductor electrode layer 50 on the other side of the gate electrode 10 and the drain electrode 20 connected to the drain layer 70. Adjacent to and lower in resistance than the semiconductor surface layer 50 and not reaching the channel portion 90 and the substrate 40 between the source layer 80 and the drain layer 70 of the semiconductor surface layer 50. Element-side connection portion 100 (see FIG. 2), which is selectively formed on the sidewall), is adjacent to the element-side connection portion 100 and has a lower resistance than the semiconductor surface layer 50. Connecting the contact side connecting portion 110 (see FIG. 3), the source layer 80, the element side connecting portion 100 and the contact side connecting portion 110 selectively formed on the semiconductor surface layer 50 so as to reach the semiconductor substrate 40. The source electrode 30 and the source electrode 31 are provided on the rear surface of the semiconductor substrate 40 so as to be connected to the semiconductor substrate 40.
[72] A semiconductor substrate such as GaAS or SiC may be used for the semiconductor substrate 40.
[73] Furthermore, the semiconductor device according to the present embodiment further includes a p-type base layer 120 formed in a tab shape around the source layer 80 and diffused into the channel portion 90 to determine the threshold voltage of the semiconductor device. Equipped. The drain layer 70 is an n ⁺ type junction 70a for resistive bonding with the drain electrode 20, and an electric field relaxation portion 70b for increasing the breakdown voltage between the source electrode 30 and the drain electrode 20. Equipped with. Further, the gate electrode 10, the drain electrode 20, and the source electrode 30 are insulated from each other by an insulating material 130 such as an oxide film such as SiO ₂ .
[74] In the present embodiment, the drain layer 70, the source layer 80, and the base layer 120 are diffusion layers. The diffusion layer is formed by selectively injecting impurities into the semiconductor surface layer 50 using a photo process or the like and diffusing the impurities by a thermal process. The same applies to the case where the element side connecting portion 100 and the contact side connecting portion 110 are diffusion layers.
[75] The contact side connecting portion 110 is formed in a tab shape so as to surround the source layer 80 around the source layer 80. The back electrode 31 is connected to the source electrode 30 via the contact side connecting portion 110 and is formed as the second source electrode 31.
[76] According to this embodiment, the impurity concentration of the p ⁺ type contact side connecting portion 110 is higher than that of the p type semiconductor surface layer 50 and the p type base layer 120. Therefore, the resistance of the contact side connecting portion 110 is lower than that of the semiconductor surface layer 50 and the base layer 120.
[77] For convenience, a portion of the semiconductor device according to the present embodiment including the element-side connection portion 100 of FIG. 2 is called the element-side semiconductor device 200, and a portion including the contact-side connection portion 110 of FIG. 3 is contacted. This is called the side semiconductor device 300.
[78] 4 is an enlarged cross-sectional view showing a cross section taken along line 4-4 'of the semiconductor device of the embodiment shown in FIG. FIG. 4 shows the semiconductor device according to the present embodiment by dividing it into parts of the element-side semiconductor device 200 and parts of the contact-side semiconductor device 300 by dotted lines.
[79] In the portion of the element-side semiconductor device 200, the element-side connection portion 100 does not reach the semiconductor substrate 40. On the other hand, in the part of the contact side semiconductor device 300, the contact side connection part 110 is largely spread | diffused and reaches the semiconductor substrate 40. FIG. The element side connecting portion 100 and the contact side connecting portion 110 are adjacent to each other and have almost the same resistivity as the semiconductor substrate 40. Moreover, the element side connection part 100 and the contact side connection part 110 are integrally formed with each other. According to this embodiment, the some element side connection part 100 and the some contact side connection part 110 are alternately arrange | positioned regularly in linear form.
[80] As shown in FIGS. 1-4, in this embodiment, the some element side connection part 100 is formed in linear form. The contact side connecting portion 110 is formed to be adjacent to the element side connecting portion 100 or to overlap the element side connecting portion 100. Moreover, in the cross section perpendicular | vertical to the linear direction of the element side connection part 100, the contact side connection part 110 is spread | diffused deeper than the element side connection part 100. FIG.
[81] Next, the operation of the semiconductor device of the present embodiment will be described. When the semiconductor device is turned ON, a predetermined voltage is applied to the gate electrode 10. As a result, the channel portion 90 under the gate electrode 10 is inverted to conduct the drain electrode 20 and the source electrode 30.
[82] The same voltage is applied to the gate electrode 10 of FIGS. 2 and 3. However, the element side connection part 100 does not reach the channel part 90 of FIG. Therefore, the channel portion 90 is mainly formed of the base layer 120. Therefore, the threshold voltage of the channel portion 90 is mainly determined by the impurity concentration of the base layer 120. On the other hand, since the contact side connection part 110 reaches the channel part 91 of FIG. 3, the channel part 91 is mainly formed by the base layer 120 and the contact side connection part 110. As shown in FIG. Therefore, the impurity concentration of the channel portion 91 of the contact side semiconductor device 300 is higher than the impurity concentration of the channel portion 90 of the element side semiconductor device 200. Therefore, the contact side threshold voltage of the contact side semiconductor device 300 is higher than the element side threshold voltage of the device side semiconductor device 200.
[83] In the present embodiment, the gate voltage applied to the gate electrode 10 is equal to or greater than the element side threshold voltage and also equal to or less than the contact side threshold voltage. Accordingly, the element side semiconductor device 200 is turned on while the contact side semiconductor device 300 is kept off. As a result, the gate device does not need a gate voltage to turn on the element-side semiconductor device 200 and the contact-side semiconductor device 300, so that the semiconductor device can flow a current at a relatively low gate voltage. The lower the gate voltage required for switching, the faster the switching speed. Therefore, the semiconductor device according to the present embodiment can cope with an input having a high frequency.
[84] In addition, not only the element-side semiconductor device 200 but also the contact-side semiconductor device 300 may be turned ON by setting the gate voltage to be equal to or higher than the contact-side threshold voltage. When the contact side semiconductor device 300 is also turned ON, the ON resistance of the semiconductor device is lowered than when only the element side semiconductor device 200 is in the ON state. However, in the ON state, the resistance of the channel portion 91 of the contact side semiconductor device 300 is higher than the resistance of the channel portion 90 of the device side semiconductor device 200. Therefore, most of the current flowing through the semiconductor device flows through the channel portion 90 of the element-side semiconductor device 200.
[85] In addition, the threshold voltage of the semiconductor device according to the present embodiment is mainly controlled by the base layer 120 and does not relate to the element side connection part 100 and the contact side connection part 110. Thus, the variation of the threshold voltage is small between wafers or between lots.
[86] When the element side semiconductor device 200 is turned on, current flows from the drain layer 70 to the source layer 80 via the channel portion 90. Thereafter, current flows from the source layer 80 to the source electrode 30. Furthermore, current flows from the source electrode 30 to the contact side connecting portion 110. Alternatively, current flows from the source electrode 30 to the element side connection portion 100 and further to the contact side connection portion 110. The current flowing to the contact side connecting portion 110 flows to the source electrode 31 through the semiconductor substrate 40.
[87] In other words, the current flows in the element-side semiconductor device 200 in the direction from the drain layer 70 to the source layer 80 in the direction of the arrow X in FIG. 1. Thereafter, the source electrode 30 or the element side connection portion 100 flows in the direction from the element side connection portion 100 to the contact side connection portion 110 (the direction of the arrow Y in FIG. 1) different from the direction of the arrow X. . In the case of this embodiment, the direction of arrow Y is substantially orthogonal to the direction of arrow X. FIG. Further, current flows from the source electrode 30 or the element side connection portion 100 to the contact side connection portion 110, and the direction from the contact side connection portion 110 to the source electrode 30 (direction of arrow Z in FIG. 4). Flows into. In the case of this embodiment, the direction of arrow Z is substantially orthogonal to the direction of arrow Y, and the direction of arrow X. FIG.
[88] In the conventional example, all the channels are formed in the channel portion 2130 so that current flows. According to the present embodiment, even when a predetermined threshold voltage is applied to the gate electrode 10, almost no current flows in the channel portion 91 of the contact-side semiconductor device 300. Therefore, the total channel width of the semiconductor device is reduced by the channel width of the channel portion 91 in the contact-side semiconductor device 300 as compared with the conventional example. When the total channel width decreases, the ON resistance rises.
[89] However, the element side connection portion 100 of the semiconductor device according to the present embodiment does not need to be diffused to reach the semiconductor substrate 40. Therefore, the width | variety of the transverse direction in the direction of the channel part 90 of the element side connection part 100 is small compared with the contact side connection part 110 or the connection layer 2160 of a conventional example. Therefore, even if the semiconductor device is reduced in size by narrowing the distance between the electrodes, the distance between each diffusion layer, or the like, the element side connecting portion 100 does not reach the channel portion 90. Therefore, since the threshold voltage of the semiconductor device according to the present embodiment does not rise due to the miniaturization of the semiconductor device, the problem due to the miniaturization of the semiconductor device does not occur. That is, according to this embodiment, the number of unit cells or element units of the semiconductor element that can be formed within a predetermined area can be increased. As a result, the total channel width of the MOSFET is increased, so the ON resistance is lowered. In addition, by miniaturizing the semiconductor device, the manufacturing cost is reduced.
[90] That is, an increase in the ON resistance due to the formation of the contact side semiconductor device 300 and a decrease in the ON resistance due to the miniaturization of the semiconductor device have a trade-off relationship.
[91] According to the area ratio of the formation of the element-side semiconductor device 200 and the contact-side semiconductor device 300, the ON resistance of the semiconductor device according to the present embodiment is lowered.
[92] For example, when the ratio of the formation area of the element-side semiconductor device 200 to the contact-side semiconductor device 300 is 19: 1, the total channel width is reduced by about 5%. Thus, the channel resistance rises by about 5%. Furthermore, according to the semiconductor device according to the present embodiment, a part of the contact layer is referred to as the contact side connection part 110 and the other part is referred to as the element side connection part 100. Therefore, the resistance between the MOSFET and the semiconductor substrate of this embodiment is high compared with the resistance between the MOSFET and the semiconductor substrate of the conventional example. Therefore, the increase rate of the ON resistance of the semiconductor device of the present embodiment, which is the sum of the increase rate of the channel resistance and the increase rate of the resistance between the MOSFET and the semiconductor substrate due to the decrease of the total channel width, is usually about 20%.
[93] On the other hand, the reduction ratio by forming the element-side semiconductor device 200 can be about 75% or less. In consideration of about 20% of the rate of increase of the ON resistance of the semiconductor device of this embodiment, the ON resistance in a certain area of this embodiment is equal to the ON resistance in a certain area of the conventional embodiment. 1.2 × 0.75 = 0.9 times. Therefore, the ON resistance of this embodiment is reduced by about 10% compared to the ON resistance of the conventional example.
[94] In a situation in which the tendency of the semiconductor device to be miniaturized more and more recently, the merit that the ON resistance can be reduced even by miniaturizing the semiconductor device is large.
[95] In addition, the contact layer 2160 is not distinguished from each other like the element-side connection part 100 and the contact-side connection part 110. Therefore, the element-side connection part was also spreading to reach the semiconductor substrate.
[96] As described above, the resistance between the MOSFET and the semiconductor substrate of this embodiment is higher than the resistance between the MOSFET and the semiconductor substrate of the conventional example.
[97] However, the ON resistance of the semiconductor device is most affected by the resistance of the channel portion 90. In the semiconductor device according to the present embodiment, the total extension of the channel portion 90 increases due to the miniaturization of the semiconductor device or the unit cell, and the channel resistance as a whole decreases. Therefore, the ON resistance as a whole of the semiconductor device according to the present embodiment is lowered.
[98] When the semiconductor device is switched from ON to OFF or from OFF to ON, a large current due to inductance or the like may be applied between the source and the drain.
[99] The contact side connecting portion 110 of the semiconductor device according to the present embodiment surrounds the source layer 80, and the resistance of the contact side connecting portion 110 is compared with that of the semiconductor surface layer 50 and the base layer 120. Low.
[100] Therefore, the avalanche current flowing between the source and the drain can easily flow through the contact side connection portion 110 directly below the source layer 80, and thus, the entire position generated between the source electrode and the contact side connection portion 110 is small. Therefore, the junction between the source layer 80 and the contact side connecting portion 110 is not forward biased. Therefore, since the semiconductor device is not destroyed by excessive current, element destruction by L load switching does not occur.
[101] In addition, in order to prevent element breakdown by L load switching, it is effective to prevent avalanche breakdown between the source and the drain of the element-side semiconductor device 200. Therefore, the breakdown voltage between the source and the drain of the contact-side semiconductor device 300 is preferably equal to or lower than the breakdown voltage between the source and the drain of the element-side semiconductor device 200.
[102] In addition, the semiconductor device according to the present embodiment can be manufactured by changing the mask of only the element-side connection portion 100 and the contact-side connection portion 110 in the conventional process.
[103] 5 is a schematic partially enlarged plan view of a second embodiment of a semiconductor device according to the present invention.
[104] FIG. 6 is a cross-sectional view taken along line 6-6 'of FIG. 5. Here, sectional drawing along the 2-2 'line | wire in FIG. 5 is the same as that shown in FIG.
[105] The semiconductor device according to the present embodiment has an element side semiconductor device 200 (see FIG. 2) and a contact side semiconductor device 302 (see FIG. 6). The device side semiconductor device 200 has a gate electrode 10, and the contact side semiconductor device 302 does not have a gate electrode. Here, sectional drawing along the 4-4 'line is the same as FIG.
[106] In the semiconductor device according to the present invention, the contact-side semiconductor device does not need to be turned ON. Therefore, the contact side semiconductor device 302 does not need to have a gate electrode. Since the gate electrode is not formed in the contact side semiconductor device 302, the capacitance of the entire gate electrode 10 or the capacitance (feedback capacitance) between the drain and the gate is reduced. Therefore, the switching speed of the semiconductor device is increased.
[107] In addition, the contact side semiconductor device 302 does not have a source layer. Therefore, parasitic bipolar transistors as shown in the conventional example of Figs. 25A and 25B are not formed. In the contact-side semiconductor device 302, a diode is formed between the drain electrode 20 and the source electrode 30 or the source electrode 31 with the drain layer 70 and the base layer 120.
[108] In the semiconductor device according to the present embodiment, the contact-side semiconductor device 302 is used as compared to the breakdown voltage of the parasitic bipolar transistor formed between the drain electrode 20 and the source electrode 30 in the element-side semiconductor device 200. The breakdown voltage of the diode formed between the drain electrode 20 and the source electrode 30 or the source electrode 31 is lower. Accordingly, even when excess power is supplied between the drain electrode 20 and the source electrode 31 of the semiconductor device, most of the current flows to the diode formed in the contact side semiconductor device 302. Therefore, element destruction by L load switching does not occur and the semiconductor device is not destroyed.
[109] Fig. 7 is an equivalent circuit diagram showing the connection relationship between the gate electrode 10, the drain electrode 20, and the source electrode 31 of the second embodiment of the semiconductor device according to the present invention.
[110] 8 is a graph showing a comparison between the breakdown voltage 801 between the source and the drain of the contact-side semiconductor device and the breakdown voltage 800 between the source and the drain of the device-side semiconductor device. The breakdown voltage 801 is collapsed at a lower voltage than the breakdown voltage 800.
[111] Therefore, when a predetermined voltage is applied to the gate electrode 10 and the semiconductor device is turned on, a current flows between the drain electrode 20 and the source electrode 31 as shown by an arrow 700. Flow 200).
[112] On the other hand, when excess power is supplied between the drain electrode 20 and the source electrode 31, the current flows between the drain electrode 20 and the source electrode 31 as shown by arrow 701 (contact side semiconductor device ( Flow 302).
[113] The presence of the contact-side semiconductor device 302 allows the semiconductor device 302 to be disposed between the drain electrode 20 and the source electrode 31 when the semiconductor device is switched from ON to OFF or from OFF to ON. Does not concentrate on the element-side semiconductor device 200. Therefore, the element side semiconductor device 200 is not destroyed.
[114] 9 is a sectional view of a third embodiment of semiconductor device according to the present invention. According to the present embodiment, the element-side semiconductor device is the same as the element-side semiconductor device 200 shown in FIG. 2 in the section along the line 2-2 'of FIG. 5, but the p-type base layer ( 120 differs from the second embodiment shown in FIG.
[115] Further, the p ⁺ -type contact side connecting portion 110 having a higher impurity concentration is formed so as to be adjacent to the electric field relaxation portion 70b. Accordingly, the diode between the drain electrode 20 and the source electrode 30 of the contact side semiconductor device 304 is formed of the p ⁺ type contact side connection portion 110 and the electric field relaxation portion 70b, and the breakdown voltage is low. have. Accordingly, the breakdown voltage of the diode between the drain electrode 20 and the source electrode 30 of the contact-side semiconductor device 304 is npn between the drain electrode 20 and the source electrode 30 of the device-side semiconductor device 200. It is below the breakdown voltage of a bipolar transistor.
[116] On the other hand, in the electric field relaxing part 70b, the amount of n-type impurities of about 1 × 10 ¹² cm ^-2 to about 5 × 10 ¹² cm ^-2 is a substantial amount of impurities obtained by subtracting the amount of p-type impurities from the amount of n-type impurities. It is preferable to exist. As a result, the depletion layer tends to be extended to the field relaxation portion 70b, and the resistance of the field relaxation portion 70b can be maintained at an appropriate value.
[117] According to this embodiment, the width | variety of the lateral direction of the diffusion layer of the field relaxation part 70b does not differ between the element side semiconductor device 200 and the contact side semiconductor device 304. FIG. Therefore, the photomask for forming the electric field relaxing part 70b of the prior art does not require a design change.
[118] 10 is a cross-sectional view of the fourth embodiment of the semiconductor device according to the present invention. According to the present embodiment, the cross-sectional view taken along the line 2-2 'of FIG. 5 is the same as that of the element-side semiconductor device 200 of FIG. 2, but is wider from the end of the junction portion 70a of the contact-side semiconductor device 306. The width Ln of the lateral direction of the electric field relaxing part 70b differs compared with 2nd Embodiment shown in FIG. That is, in the electric field relaxing part 70b of the contact side semiconductor device 306, the width | variety Ln of the lateral direction to the channel part 91 is smaller than the electric field relaxation part 70b of the element side semiconductor device 200. FIG. Therefore, when a voltage is applied to the drain electrode 20, the depletion of the depletion layer in the field relaxation portion 70b of the contact side semiconductor device 306 is smaller than that of the element side semiconductor device 200. Accordingly, the drain electrode 20 and the source electrode 30 of the contact-side semiconductor device 306 are higher than the breakdown voltage of the npn bipolar transistor between the drain electrode 20 and the source electrode 30 of the element-side semiconductor device 200. The breakdown voltage of the diode is made low.
[119] 11 and 12 are cross-sectional views of a fifth embodiment in which a metal plug is used for a contact side connection portion as a semiconductor device according to the present invention. FIG. 11 corresponds to a cross section taken along the line 2-2 'of FIG. 5, and FIG. 12 corresponds to a cross section taken along the line 6-6' of FIG. The contact side connecting portion 112 of FIG. 12 is formed of a metal plug 112. The contact side connecting portion 112 electrically connects the source electrode 30 and the semiconductor substrate 40. The metal plug 112 has the same effect as the contact side connecting portion 110 of the first to fourth embodiments formed by the p ⁺ type diffusion layer.
[120] Since the metal plug 112 has a lower resistance than the diffusion layer, the ON resistance of the semiconductor device is lowered. In addition, since the metal plug 112 does not need to be diffused, a contact side connection portion can be formed in a region narrower than the diffusion layer. Therefore, the semiconductor device using the metal plug 112 in the contact side connection portion has a lower ON resistance and can be downsized than the semiconductor device using the diffusion layer.
[121] However, the contact side semiconductor device 307 of FIG. 12 has a junction portion 70a, an electric field relaxation portion 70b, and a base layer 120 which are almost the same as the element side semiconductor device 202 of FIG. Therefore, the breakdown voltage between the source and the drain of the contact-side semiconductor device 307 is substantially the same as the breakdown voltage between the source and the drain of the element-side semiconductor device 202. Therefore, when the power semiconductor device is formed by the combination of the contact side semiconductor device 307 and the element side semiconductor device 202, element destruction due to L load switching cannot be prevented.
[122] 13A, 13B, 14A, and 14B show another embodiment of the element-side semiconductor device 202 or the contact-side semiconductor device 307 shown in FIG. 11 or 12 among the fifth embodiments having the metal plug 112. Indicates. 13A, 13B, and 14A show another embodiment of the contact-side semiconductor device 307, respectively, and FIG. 14B shows another embodiment of the element-side semiconductor device 202.
[123] The contact side semiconductor device 308 shown in FIG. 13A differs from the contact side semiconductor device 307 in FIG. 12 in that it has a wider width in the transverse direction (direction toward the channel) of the junction 70a of the drain. Do.
[124] Therefore, the width Ln of the lateral direction of the electric field relaxing portion 70b widening from the end of the junction portion 70a of the contact side semiconductor device 308 is determined by the contact side semiconductor device 307 and the element side semiconductor device 202. It becomes narrower than the width | variety Ln of the lateral direction of the electric field relaxation part 70b which expands from the end of the junction part 70a. Therefore, when a voltage is applied between the source and the drain, the depletion layer widening between the field relaxing part 70b and the base layer 120 in the contact-side semiconductor device 308 is a contact-side semiconductor device ( 307 and narrower than the depletion layer widening between the field relaxing part 70b and the base layer 120 in the element side semiconductor device 202. Therefore, the breakdown voltage between the source and the drain of the contact-side semiconductor device 308 is lower than the breakdown voltage between the source and the drain of the contact-side semiconductor device 307 and the element-side semiconductor device 202.
[125] Therefore, when the power semiconductor device is formed by the combination of the contact side semiconductor device 308 and the element side semiconductor device 202, most of the avalanche current of the power semiconductor device passes through the contact side semiconductor device 308. Therefore, the ON resistance of the power semiconductor device is lowered and the element side semiconductor device 202 is protected.
[126] However, an n ⁺ type source layer 80 is formed in the contact side semiconductor device 308. Accordingly, parasitic npn bipolar transistors exist in the contact-side semiconductor device 308. Accordingly, the parasitic npn bipolar transistor is turned on by the avalanche current passing through the base layer 120 directly below the source layer 80. As a result, the element of the contact-side semiconductor device 308 is destroyed.
[127] The contact side semiconductor device 309 shown in FIG. 13B differs in that there is no n ⁺ type source layer 80 as compared with the contact side semiconductor device 308 in FIG. 13A. Since there is no source layer 80 in the contact-side semiconductor device 309, the parasitic npn bipolar transistor does not exist in the contact-side semiconductor device 309. A diode exists between the source and the drain of the contact-side semiconductor device 309. Therefore, even if the avalanche current passes between the source and the drain of the contact-side semiconductor device 309, the element of the contact-side semiconductor device 309 is not destroyed.
[128] Therefore, when the power semiconductor device is formed by the combination of the contact side semiconductor device 309 and the element side semiconductor device 202, the ON resistance of the power semiconductor device is lowered to protect the element side semiconductor device 202. In addition, the element of the contact-side semiconductor device 309 is not destroyed.
[129] The contact-side semiconductor device 311 shown in FIG. 14A has no p-type base layer 120 as compared with the contact-side semiconductor device 309 in FIG. 13B. Therefore, the contact side semiconductor device 311 is formed with a simpler structure than the contact side semiconductor device 309. In addition, compared with the contact-side semiconductor device 309, the width in the transverse direction toward the channel of the field relaxation portion 70b and the junction portion 70a of the drain layer 70 is wider, and the field relaxation portion 70b contacts. It differs in the point which is formed in contact with the side connection part 110. FIG. On the other hand, compared with the contact side semiconductor device 309, the width | variety Ln of the lateral direction of the electric field relaxation part 70b from the end of the junction part 70a may be the same.
[130] Therefore, when the power semiconductor device is formed by the combination of the contact side semiconductor device 311 and the element side semiconductor device 202, the power semiconductor device is formed of the contact side semiconductor device 309 and the element side semiconductor device 202. It has the same effect as when formed in combination.
[131] On the other hand, the contact side semiconductor devices 307, 308, 309 and 311 have a gate electrode 10. As shown in FIG. However, the gate electrode 10 does not need to be formed on the contact side semiconductor devices 307, 308, 309, and 311. Without the gate electrode 10 of the contact-side semiconductor device, since the capacitance of the gate electrode 10 is lost, the switching speed of the power semiconductor device is increased.
[132] In the semiconductor device according to the present embodiment, the element-side connection part is a diffusion layer and the contact-side connection part is a metal plug. However, you may form a metal plug along the whole 4-4 'line | wire of FIG. That is, a metal plug may be used for the element side connection portion of the element side semiconductor device.
[133] For example, FIG. 14B is a sectional view of an embodiment of an element-side semiconductor device 204 using a metal plug in an element-side connection portion.
[134] The device side semiconductor device 204 has a metal plug 102 between adjacent source layers 80. The metal plug 102 is connected to the metal plug 112 in the contact side semiconductor devices 307, 308, 309, and 311. Therefore, the metal plug is formed along the entirety of the 4-4 'line | wire of FIG.
[135] On the other hand, since the source electrode 30 is connected to the element-side connecting portion 100, the distance between adjacent source layers 80 must be wider than the width of the metal plug 102. This means that if the distance between adjacent source layers 80 is made smaller than the width of the metal plug 102, the source electrode 30 cannot be connected to the element-side connection portion 100, and as a result, the implementation shown in FIG. 14B is performed. This is because it is difficult to miniaturize the semiconductor device.
[136] In the case where the element-side semiconductor device 202 of FIG. 11 is formed, even if the distance between the adjacent source layers 80 is narrowed, since there is no metal plug, the source electrode 30 has both elements of the adjacent source layer 80 and the elements. It may be connected to the side connection portion 100. In the contact-side semiconductor device 307 of FIG. 12, the distance between the adjacent source layers 80 may be small, so that the source electrode 30 may not be connected to the element-side connection portion 100. This is because the connection between the source electrode 30 and the source layer 80 and the element side connecting portion 100 is secured in the element side semiconductor device 202.
[137] Therefore, the power semiconductor device formed of the element-side semiconductor device 202 of FIG. 11 and the contact-side semiconductor device 307 of FIG. 12 can be made smaller than the power semiconductor device formed of using the element-side semiconductor device 204 of FIG. 14B. Can be.
[138] Therefore, among the fifth embodiments shown in FIGS. 11 to 13, a power semiconductor device formed by the combination of the element-side semiconductor device 202 and the contact-side semiconductor device 309 or 311 is preferable in view of the effects of the present embodiment. Do.
[139] However, other forms may be adopted in consideration of the manufacturing process, manufacturing cost, and the like.
[140] On the other hand, in the contact side semiconductor device 308, 309 or 311, the width | variety of the lateral direction of the junction part 70a is comparatively large. Therefore, the width Ln in the lateral direction of the field relaxation portion 70b that extends from the end of the junction portion 70a is narrower than that of the field relaxation portion 70b of the element-side semiconductor device 202 or 204.
[141] However, the width in the lateral direction of the junction portion 70a of the contact side semiconductor device 308, 309 or 311 and the element side semiconductor device 202 or 204 may be the same. In this case, the width Ln of the lateral direction of the electric field relaxing portion 70b that extends from the end of the junction portion 70a in the contact side semiconductor device 308, 309 or 311 is determined by the element side semiconductor device 202 or 204. In order to make it narrower than the field relaxation part 70b, the width | variety of the field relaxation part 70b itself may be made narrow, without changing the width of the junction part 70a in the lateral direction. Accordingly, the breakdown voltage between the source and the drain of the contact side semiconductor device 308, 309 or 311 can be lower than the breakdown voltage between the source and the drain of the device side semiconductor device 202 or 204.
[142] However, it is necessary to widen the width of the base layer 120 in the transverse direction so that the base layer 120 is in contact with the electric field relaxing part 70b. As a result, the breakdown voltage between the source and the drain of the contact-side semiconductor device 308, 309 or 311 is lower than the breakdown voltage between the source and the drain of the element-side semiconductor device 202 or 204.
[143] In addition, in this embodiment, the metal plugs 102 and 112 may be formed with the same material in the same process. Since the metal plugs 102 and 112 are connected to each other, in this case the metal plugs 102 and 112 can be recognized as substantially the same.
[144] On the other hand, the metal plugs 102 and 112 may be formed of different materials in separate processes. In this case, the metal plugs 102 and 112 may be connected by interconnection wiring.
[145] 15 and 16 are cross-sectional views of a semiconductor device having a drain electrode on its back side as a sixth embodiment of the semiconductor device according to the present invention. According to this embodiment, the semiconductor substrate 40 is n ⁺⁺ type. The drain electrode 20 is formed on the rear surface of the semiconductor substrate 40 so as to be connected to the semiconductor substrate 40. The metal plugs 104 and 114 penetrate through the semiconductor surface layer 50 from the drain layer 70 to the semiconductor substrate 40. As a result, the drain layer 70, the semiconductor substrate 40, and the drain electrode 20 on the back surface are connected.
[146] In order to insulate between the metal plugs 104 and 114 and the semiconductor surface layer 50, a plug insulator 115 is formed around the metal plugs 104 and 114. As the plug insulator 115, an n-type semiconductor layer or SiO ₂ is used. For example, n-type impurities such as As and P are driven in an inclined direction with respect to the sidewalls of the trench in which the metal plugs 104 and 114 are embedded. Thereafter, an n-type semiconductor layer is formed by diffusing impurities by heat treatment. The n-type semiconductor layer is insulated between the metal plugs 104 and 114 and the semiconductor surface layer 50. In addition, the plug insulator 115 may be a residue such as SiO ₂ formed on the sidewall of the trench during etching of the trench.
[147] The contact side semiconductor device 310 shown in FIG. 16 does not have a source layer 80. Accordingly, it is possible to prevent the parasitic npn bipolar transistor from being turned on by the avalanche current and destroying the semiconductor element of the contact-side semiconductor device 310.
[148] The junction 70a of the drain of the contact-side semiconductor device 310 is formed to have a wider width in the lateral direction than the junction 70a of the device-side semiconductor device 210. As a result, in the electric field relaxation portion 70b of the contact side semiconductor device 310, the width Ln in the lateral direction that is wider from the end of the junction portion 70a than the electric field relaxation portion 70b of the element side semiconductor device 210 is. Narrows. Accordingly, the breakdown voltage between the source and the drain of the contact-side semiconductor device 310 can be lower than the breakdown voltage between the source and the drain of the element-side semiconductor device 210.
[149] Moreover, the depth and impurity concentration of each of the element-side connection part 100 and the contact-side connection part 110 are almost the same. Therefore, the element side connection part 100 and the contact side connection part 110 can be formed simultaneously.
[150] The source electrode 30 is formed on the surface of the semiconductor substrate 40. Further, the source electrode 30 is formed so as to cover the insulating material 130.
[151] The semiconductor surface layer 50 may be n-type. However, the concentration of the n-type semiconductor surface layer 50 is preferably lower than that of the electric field relaxing part 70b. This is because the internal pressure between the source and the drain can be determined by the width Ln in the transverse direction of the electric field relaxing part 70b that extends from the end of the junction part 70a.
[152] In the present embodiment, the metal plugs 104 and 114 may be formed of the same material in the same process. Since the metal plugs 104 and 114 are connected to each other, in this case the metal plugs 104 and 114 can be recognized as substantially the same.
[153] On the other hand, the metal plugs 104 and 114 may be formed of different materials in separate processes. In this case, the metal plugs 104 and 114 may be connected by wiring.
[154] In the semiconductor devices according to the fifth and sixth embodiments, the metals used for the metal plugs 102, 104, 112, and 114 are tungsten, aluminum, copper, Al-Si, Al-Si-Cu, and the like.
[155] Instead of the metal plugs 102, 104, 112 and 114, a nonmetallic material may be used. As the plug of the nonmetal material, doped polysilicon may be used. In this case, after the trench is formed at a position where a predetermined plug is formed, impurities are embedded in the trench at an angle before the plug is embedded. This lowers the resistance of the sidewalls of the trench. Thereafter, by embedding the plug, a side wall conductive layer (not shown) is formed around the plug. The side wall conductive layer electrically connects the drain layer 70 or the source electrode 30 to the semiconductor substrate 40 and the drain electrode 20 or the source electrode 31 on the back side.
[156] Furthermore, in the first to sixth embodiments according to the present invention, the gate electrode 10, the drain layer 70, the source layer 80, the element side connection portion 100, the contact side connection portion 110, and the source, respectively, An element unit 1000 (refer to FIG. 1 or FIG. 5) including an electrode 30 and a drain electrode 20 is formed. The element units 1000 adjacent to each other share either the source electrode 30 or the drain electrode 20. Therefore, source electrodes or drain electrodes of the plurality of element units 1000 are connected in parallel. Therefore, as the number of device units 1000 increases, the total channel width increases, so that a large current can flow between the source and the drain.
[157] In the first to sixth embodiments of the present invention, as shown in FIG. 1 or FIG. 5, the element unit 1000 connects the plurality of element side connection portions 100 and the plurality of contact side connection portions 110. Connection rows arranged alternately in a straight line shape (overlapping under the source electrode 30) and drain lines arranged in a straight line with the drain layer 70 overlapping under the drain electrode 20. Has The adjacent connection columns are formed in substantially the same manner as the plurality of source electrodes 30 adjacent to each other. Like the drain electrode 20, the drain column is formed in parallel with the connection row between the connection rows adjacent to each other.
[158] In this manner, by aligning the elements, reduction in size due to the design change of the semiconductor device becomes easy, and integration of the semiconductor device becomes easy.
[159] 17A and 17B are schematic partial enlarged plan views of an embodiment different from the embodiment shown in FIGS. 1 and 5 of the semiconductor device according to the present invention. In the semiconductor device according to the present embodiment, the plurality of element-side connection portions 100 are formed in a straight line along the line E-E '. The contact side connecting portion 110 is formed along the line D-D '. In FIG. 17A, the element side connection part 100 and the contact side connection part 110 extend under the source electrode 30. In addition, the plurality of drain layers 70 is formed in a straight line parallel to the line E-E '. The drain layer 70 extends under the drain electrode 20.
[160] The contact side connection part 110 is formed in the direction perpendicular to the arrangement direction of the element side connection part 100 and the drain layer 70. In addition, the contact side connecting portion 110 is formed to contact the element side connecting portion 100 between the plurality of element side connecting portions 100 arranged in a linear shape, and the junction portion of the drain between the plurality of drain layers 70. It is formed in the vicinity so as not to contact 70a.
[161] In addition, one long element side connection portion 100 and a drain layer 70 may be formed in a linear shape, and the plurality of contact side connection portions 110 may be arranged in a linear shape. In this case, the element side connecting portion 100 is formed to contact the contact side connecting portion 110 between the plurality of contact side connecting portions 110. The drain layer 70 is formed in the vicinity of the plurality of contact side connection portions 110 such that the junction portion 70a does not contact the contact side connection portion 110.
[162] In addition, in this embodiment, although the element side connection part 100, the contact side connection part 110, and the drain layer 70 are formed in linear form, they may be curved.
[163] The hatched portions of the gate electrode 10, the drain electrode 20, and the source electrode 30 shown in Figs. 17A and 17B are respectively a junction portion of the gate electrode 10 and the gate wiring 111 and the drain electrode ( 20 and a junction portion of the drain layer 70 and a junction portion of the source electrode 30 and the source layer 80, the element side connection portion 100, or the contact side connection portion 110. FIG.
[164] FIG. 17B differs from FIG. 17A in that no portion of the source electrode 30 along the line D-D 'is formed. The contact side connecting portion 110 is formed along the line D-D 'similarly to Fig. 17A. On the other hand, since the portion of the source electrode 30 is not formed along the line D-D ', it is preferable in that the parasitic capacitance between the source electrode 30 and the drain electrode 20 or the gate electrode 10 is reduced. .
[165] 18 is a cross-sectional view taken along line C-C 'of the device-side semiconductor device 220 according to the embodiment of FIG. 17A or 17B. The source electrode 30 is connected to the source layer 80 and the element side connection part 100. The element side connecting portion 100 does not reach the semiconductor substrate 40.
[166] 19A and 19B are sectional views taken along the line D-D 'of the contact-side semiconductor device 320 according to the embodiment of FIG. 17A, in which a metal plug is used for the contact-side connection portion. The metal plug 116 reaches the semiconductor substrate 40. In addition, the metal plug 116 is formed over the left and right of FIG. Therefore, the metal plug 116 is perpendicular to the drain electrode 20, that is, the drain layer 70. The source electrode 30 is connected to the metal plug 116. Here, the cross-sectional view taken along the line D-D 'of FIG. 17B is a shape in which no portion of the source electrode 30 is shown in FIG.
[167] On the other hand, the drain electrode 20 is formed on the insulating material 130 in FIG. In this embodiment, the drain electrode 20 overlaps with the metal plug 116 as the contact side connecting portion. However, as shown in FIG. 19B, the semiconductor device according to the present embodiment may be designed so that the drain electrode 20 does not overlap with the metal plug 116. FIG. Since the drain electrode 20 and the metal plug 116 do not overlap, the capacitance between the source and the drain can be reduced.
[168] 20 is a cross-sectional view taken along the line E-E 'of FIG. 17A or 17B of an embodiment in which a metal plug is used for a contact side connecting portion. It can be seen that the metal plug 116 is reaching the semiconductor substrate 40. In addition, the element-side connecting portion 100 extends along the line E-E 'and is connected to the metal plug 116. Therefore, according to this embodiment, the element side connection part 100 and the metal plug 116 orthogonally cross.
[169] When the semiconductor device according to the present embodiment is in an ON state, a current is generated between the source electrode 30 according to E-E 'of FIG. 17 and the drain electrode 20 formed in parallel to E-E'. Flow. Further, it flows from the source electrode 30 to the source electrode 31 formed on the back surface of the semiconductor substrate 40 via the metal plug 116 along the line D-D '.
[170] 21A and 21B are enlarged cross-sectional views taken along line F-F 'of the power semiconductor device shown in FIG. 17A. FIG. 21A is an enlarged cross-sectional view of a power semiconductor device having a contact-side semiconductor device 309 'having the same configuration as that of the contact-side semiconductor device 309 shown in FIG. 13B. The contact side semiconductor device 309 'includes contact side connection portions 110 and a base layer 120 on both sides of the metal plug 116 as in FIG. 13B. Thus, the base layer 120 and the drain layer 70 constitute a diode. It is preferable to keep the breakdown voltage of this diode lower than the breakdown voltage of the parasitic npn bipolar transistor of the element-side semiconductor device 220. That is, the width Ln in the lateral direction of the field relaxation portion 70b widening from the junction portion 70a of the contact-side semiconductor device 309 'is that of the field relaxation portion 70b widening from the junction portion 70a of FIG. It is preferable that it is shorter than the width | variety Ln of a horizontal direction. Accordingly, the avalanche current generated by L load switching or the like is sourced through the diode and metal plug 116 formed in the contact-side semiconductor device 309 'from the drain electrode 20 near the D-D' line. Flows). Therefore, the element-side semiconductor device (part corresponding to C-C 'in Fig. 17A) is protected. That is, also in this embodiment, it has an effect similar to 1st-6th embodiment.
[171] FIG. 21B is an enlarged cross-sectional view of the power semiconductor device having the contact-side semiconductor device 311 ′ having the same configuration as the contact-side semiconductor device 311 shown in FIG. 14A. The contact-side semiconductor device 311 'is the same in that the contact-side connection portions 110 are provided on both sides of the metal plug 116 as compared with the contact-side semiconductor device 309', but differ in that they do not have a base layer. . The contact side connecting portion 110 and the drain layer 70 are configured to form a diode. It is preferable to keep the breakdown voltage of this diode lower than the breakdown voltage of the parasitic npn bipolar transistor of the element-side semiconductor device 220. That is, the width Ln in the lateral direction of the field relaxation portion 70b widening from the junction portion 70a of the contact-side semiconductor device 311 'is equal to that of the field relaxation portion 70b widening from the junction portion 70a of FIG. It is preferable that it is shorter than the width | variety Ln of a horizontal direction. Accordingly, the avalanche current generated by L load switching or the like is transferred from the drain electrode 20 near the line D-D 'to the semiconductor electrode 311' formed on the contact-side semiconductor device 311 'via the source electrode (116). 31). Therefore, the element-side semiconductor device (part corresponding to C-C 'in Fig. 17A) is protected. That is, also in this embodiment, it has an effect similar to 1st-6th embodiment.
[172] 17B is an enlarged cross-sectional view along the line F-F 'of the power semiconductor device shown in FIG. 17B in that there is no source electrode 30 of the contact-side semiconductor devices 309' and 311 'shown in FIGS. 21A and 21B, respectively. different. However, the other configuration of the enlarged cross-sectional view along the line F-F 'of the power semiconductor device shown in Fig. 17B may be the same as that of the contact side semiconductor devices 309' and 311 '. This has the same effect as that of the first to sixth embodiments.
[173] 22A and 22B are enlarged cross-sectional views taken along line D-D 'of the contact-side semiconductor device 322 according to the embodiment of FIG. 17A, using a diffusion layer at the contact-side connection portion. The cross section of the element side semiconductor device is the same as the cross section of the element side semiconductor device 220 shown in FIG. On the other hand, the contact side semiconductor device 322 uses a contact side connecting portion 110 formed by a diffusion layer instead of the metal plug of the contact side semiconductor device 320 shown in FIG. Therefore, in the cross section of the contact side semiconductor device 322, the part of the metal plug 116 shown in FIG. 18 is the contact side connection part 110 formed by the diffusion layer.
[174] In addition, a drain electrode 20 is formed on the insulating material 130 of FIG. 22A. In the present embodiment, the drain electrode 20 overlaps with the contact side connecting portion 110. However, as shown in FIG. 22B, the drain electrode 20 may be designed so as not to overlap with the contact side connecting portion 110. FIG. Since the drain electrode 20 and the contact side connecting portion 110 do not overlap, the capacitance between the source and the drain can be reduced. In addition, also in embodiment of FIG. 17B, a diffusion layer can be used for a contact side connection part. In this case, the enlarged cross-sectional view along the line D-D 'is in a state without the source electrode 30 in Fig. 22A or 22B.
[175] FIG. 23 is a cross-sectional view taken along the line E-E 'of the embodiment of FIG. 17A or 17B in which a diffusion layer is used for the contact side connection portion. It can be seen that the contact side connecting portion 110 using the diffusion layer is formed in the portion of the metal plug 116 in FIG. 20.
[176] The semiconductor device according to the present invention can be applied not only to the DC-DC converter of the synchronous rectification circuit system but to all of the power semiconductor devices corresponding to the high frequency.
[177] Further, the semiconductor device according to the present invention can be applied to a semiconductor device used in a situation where a large power is applied regardless of the presence or absence of inductance.
[178] The semiconductor device according to the present invention can be applied to a switching power MOSFET and a rectifying power MOSFET.
[179] Furthermore, when applied to rectification power MOSFETs, a Schottky diode may be connected in parallel between the source and the drain. This enables current to flow even when the switching of the rectifying power MOSFET is delayed. Thus, the Schottky diode compensates for the rectifying power MOSFET and acts as a bypass.
[180] 27 is a partially enlarged plan view of a semiconductor device of a seventh embodiment of a semiconductor device according to the present invention. 27 is a plan view of the MOSFET chip viewed from above, and is schematically shown for easy understanding. In the first to sixth embodiments, the contact side connecting portion 110 was formed under the source electrode (short electrode) 30. However, in the following seventh to tenth embodiments, the p ⁺ type region (second semiconductor region) corresponding to the contact side connection portion is different in that it is formed under the gate electrode or the gate wiring (see FIG. 30). ). Therefore, for convenience, the p ⁺ type region formed under the gate electrode or the gate wiring among the semiconductor devices after the seventh embodiment is called the wiring side connecting portion, and the portion including the wiring side connecting portion is called the wiring side semiconductor device.
[181] In this embodiment, the MOSFET chip includes a bonding pad 762 of the gate, a gate connection pattern 763, a gate wiring 764, and a drain electrode 784. The bonding pads 762 are continuously connected to the gate connection pattern 763 in a pattern of the same layer. Vias 765 are formed in the insulating layer below the bonding pad 762 and the gate connection pattern 763. A bonding pad 762 or a gate connection pattern 763 is connected to an end of the gate wiring 764 by the via 765. The gate wiring 764 is electrically connected to the gate electrode 777 (see FIGS. 28 and 29).
[182] More specifically, the bonding pads 762 applied to the connection with the outside are connected to the bonding pads 762 by the gate connection pattern 763 and the gates through the gate wiring 764 via the vias 765. It is connected to the electrode 777.
[183] The bonding pads 762, the gate connection patterns 763, and the gate wirings 764 are formed of metal, for example, aluminum, to reduce the resistance to the gate electrode 777.
[184] On the other hand, the gate electrode 777 is not shown in FIG. 27, but is formed to be orthogonal to the gate wiring 764. The width of the gate wiring 764 is about 2 μm to 4 μm. The interval between the gate wirings 764 is about 50 μm to about 200 μm.
[185] A drain electrode 784 is formed between the adjacent gate wirings 764. The drain electrode 784 on the gate wiring 764 is removed to reduce the parasitic capacitance between the gate wiring 764 and the drain electrode 784.
[186] FIG. 28 is an enlarged plan view of the dotted line W shown in the MOSFET chip of FIG. 27. The gate wiring 764 extends laterally with respect to the ground of FIG. The drain electrode 784 is formed to be spaced apart from the gate wiring 764 around the gate wiring 764. That is, the drain electrode 784 is not formed above the gate wiring 764. As a result, the parasitic capacitance between the gate and the drain becomes small.
[187] The gate wiring 764 is connected to the gate electrode 777 through the contact hole 766. The gate electrode 777 is formed of polysilicon, metal silicide, or the like. The gate electrode 777 is composed of a gate electrode 777a connected to the gate wiring 764 and a gate electrode 777b extending almost perpendicular to the gate electrode 777a. The gate electrode 777a and the gate electrode 777b are patterns of the same layer. Here, the gate electrode 777a is formed to connect the gate electrode 777b to the gate wiring 764, and the portion between the contact hole 766 and the contact hole 766 may be removed. By doing so, parasitic capacitance between gate and source can be reduced.
[188] Below the drain electrode 784, a gate electrode 777b, a shorting electrode 782, and a drain electrode 781 are present. The short electrode 782 and the drain electrode 781 extend substantially in parallel with the gate electrode 777b. That is, the short electrode 782 is formed on one side of the gate electrode 777b and the drain electrode 781 is formed on the other side of the gate electrode 777b. In Fig. 28, the gate wiring 764, the gate electrodes 777a and 777b, and the drain electrode 781 are hatched.
[189] The gate wiring 764 is connected to the gate electrode 777a via the contact hole 766.
[190] The drain electrode 784 is connected to the drain electrode 781 via the contact hole 788. Further, the drain electrode 781 is connected to the n ⁺ type junction 778 which is a part of the drain layer via the contact plug 789.
[191] The shorting electrode 782 is connected to an n ⁺ type source layer 774 via a contact plug 790. Here, the source layer 774 has a comb-tooth shaped shape with a protrusion 774A on the plane of the semiconductor substrate. The short circuit electrode 782 is connected to the source layer 774 by contacting the protrusion 774A. As a result, the avalanche content is improved. That is, device destruction by L load switching hardly occurs.
[192] 29 is a cross-sectional view of the device-side semiconductor device 252 along the line A-A in FIG. A configuration of the semiconductor device according to the present embodiment will be described in more detail with reference to FIG. 29.
[193] The element-side semiconductor device 252 according to the present embodiment is epitaxially grown on the low-resistance p ⁺ type silicon semiconductor substrate 771 and the surface of the semiconductor substrate 771, and has a higher resistance than that of the semiconductor substrate 771. p ^- type silicon epitaxial layer 772 is provided. The thickness of the silicon epitaxial layer 772 is about 3 μm.
[194] The p-type body region 773 is selectively formed on the surface of the silicon epitaxial layer 772. A portion of the surface of the body region 773 acts as a channel region of the semiconductor device. An n ⁺ type source layer 774 and an n type drift layer (also referred to as an electric field relaxing portion) 775 are selectively formed so as to face each other with the channel region interposed therebetween. On the body region 773 between the source layer 774 and the drift layer 775, that is, on the channel region, a gate insulating film 776 made of a silicon oxide film is formed. A gate electrode 777b is formed on the gate insulating film 776. An n ⁺ type junction 778 is optionally formed in the drift region 775. The drain layer is composed of the drift region 775 and the junction 778.
[195] Under the source region 774, a p ⁺ type element side connection portion 780a is formed. The element side connection portion 780a reaches the semiconductor substrate 771 from the surface of the epitaxial layer 772. The short electrode 782 is formed in contact with the source layer 774 and the connection portion 780a to electrically connect them. 29 illustrates a cross section of the protrusion 774A in the source layer 774. Therefore, the source layer 774 is in contact with the short circuit electrode 782.
[196] A drain electrode 781 is connected to the junction portion 778 via a contact plug 789.
[197] Further, an interlayer insulating film 783 is formed above the epitaxial layer 772. A drain electrode 784 is formed on the interlayer insulating film 783. The drain electrode 784 is connected to the drain electrode 781 and is electrically connected to the junction portion 778 via a contact plug 789.
[198] A source electrode 785 is formed on the back surface of the semiconductor substrate 771. The source electrode 785 is connected to the semiconductor substrate 771. Therefore, the source layer 774 is electrically connected to the source electrode 785 through the short circuit electrode 782, the connection portion 780, and the semiconductor substrate 771. On the other hand, although the gate wiring 764 does not exist in the cross section along the line A-A 'of FIG. 28, the state through which the gate wiring 764 is transparent is shown by the dotted line in FIG.
[199] The element side semiconductor device 252 differs from the element side semiconductor device 200 in FIG. 2 in the element side connecting portion 100. Although the element side connecting portion 100 of the element side semiconductor device 200 in FIG. 2 does not reach the semiconductor substrate 40, the element side connecting portion 780a of the element side semiconductor device 252 is the semiconductor substrate 771. Is reaching. As a result, in the present embodiment, the ON resistance per unit cell is lower than in the embodiment in which only the contact connecting portion has reached the semiconductor substrate. Further, even when the drift layer 775 is locally narrow in the transverse direction due to variations in the manufacturing process and the internal pressure of the element-side semiconductor device 252 is lowered, the element-side connection portion 780a is relatively easy. An electric charge can flow to the semiconductor substrate 771.
[200] Here, the drain electrode 784 and the source electrode 785 are the main electrodes. The shorting electrode 782 is formed to short the source region 774 and the connection portion 780a.
[201] 30 is a cross-sectional view of the wiring-side semiconductor device 352 along the line B-B in FIG. As described above, the drain electrode 784 above the gate wiring 764 is removed along the gate wiring 764 to reduce the parasitic capacitance between the gate and the drain.
[202] A wiring insulating film 786 is formed under the gate electrode 777a. A wiring side connection portion 780b is formed below the gate electrode 777a. The wiring side connecting portion 780b extends along the gate wiring 764 and the gate electrode 777a below the gate wiring 764 and the gate electrode 777a. That is, the wiring side connecting portion 780b is almost orthogonal to the element side connecting portion 780a. Thus, the surface area of the semiconductor substrate can be effectively used without waste, and the semiconductor device can be further miniaturized. Furthermore, the element side connecting portion 780a and the wiring side connecting portion 780b may be formed at the same depth. Therefore, the element side connecting portion 780a and the wiring side connecting portion 780b can be formed in the same manufacturing process. Therefore, this embodiment is easier to manufacture than other embodiments.
[203] The wiring insulating film 786 is formed thicker than the gate insulating film 776. The gate insulating film 776 is about 30 탆, whereas the thickness of the wiring insulating film 786 is about 100 nm to 300 nm. The parasitic capacitance between the gate electrode 777a and the wiring side connecting portion 780b is reduced by the wiring insulating film 786 thicker than the gate insulating film 776. As a result, the parasitic capacitance between the gate and the source of the semiconductor device is reduced.
[204] The drift layer 775 has a lightly doped drain (LDD) structure. The drift layer 775 serves as the electric field relaxing part 775. Therefore, the breakdown voltage of the element-side semiconductor device 252 is almost determined according to the length of the drift layer 775 in the lateral direction. When the lateral length of the drift layer 775 is about 1 µm, the breakdown voltage of the element-side semiconductor device 252 is about 30V to about 40V.
[205] The drift layer 775 is formed by ion implantation of n-type impurities such as phosphorus (P) or arsenic (As). The amount of impurities injected into the drift layer 775 is about 2 × 10 ¹² to about 4 × 10 ¹² cm ⁻² . In the cross section shown in Fig. 29, end portions of the drift layer 775 are formed in a self-aligning manner with the gate electrode 777b as a mask.
[206] The drift layer 775 has a depth of about 0.1 µm to about 0.2 µm, and is formed relatively shallowly. Therefore, since the area where the drift layer 775 and the gate electrode 777b face is small, the capacitance between the drain and the gate is small. Therefore, by adopting the LDD structure, the semiconductor device according to the present embodiment has a high switching speed and a small switching loss.
[207] The junction 778 needs to be ohmic-joined with the contact plug 789. Therefore, the concentration of n-type impurities on the surface of the junction 778 is about 1 × 10 ¹⁸ cm ⁻³ or more, preferably about 1 × 10 ¹⁹ cm ⁻³ or more.
[208] When the breakdown voltage of the element-side semiconductor device 252 may be 10 V or less, the n ⁺ type junction 778 is formed in a self-aligning manner with the gate electrode 777b as a mask without forming the drift layer 775. do.
[209] The thickness of the interlayer insulating film 783 between the short electrode 782 and the drain electrode 784 is set to 1 µm or more. As a result, the parasitic capacitance between the short-circuit electrode 782 and the drain electrode 784 is reduced. However, when the interlayer insulating film 783 between the short electrode 782 and the drain electrode 784 is too thick, the aspect ratio (aspect ratio) of the contact hole 788 becomes too large. As a result, the embedding of the drain electrode 784 in the contact hole 788 worsens, and the resistance value of the drain electrode 784 increases. The increase in the resistance value of the drain electrode 784 increases the ON resistance of the element-side semiconductor device 252. Therefore, there is an upper limit to the film thickness of the interlayer insulating film 783 between the short circuit electrode 782 and the drain electrode 784.
[210] The thickness of the drain electrode 784 is 4 µm or more, preferably 6 µm or more. The thickness of the semiconductor substrate 771 is thinned to 100 mu m or less. As a result, the ON resistance of the element-side semiconductor device 252 is reduced.
[211] The channel region of the element-side semiconductor device 252 is formed including the p ^- type epitaxial layer 772 as well as the p-type body region 773. The body region 773 is formed by ion implantation and thermal diffusion of p-type impurities (eg, boron). The body region 773 is formed in a step before the step of forming the gate electrode 777. At that time, only about half of the source layer 774 side of the lower portion of the gate electrode 777b formed later is implanted with impurities, and about half of the drain layer side does not implant ions. As a result, the p-type impurity concentration is gradually lowered toward the drain side end (the end of the drift layer 775) of the channel region. Therefore, in the element-side semiconductor device 252, the depletion layer extending from between the body region 773 and the drift layer 775 extends not only in the drift layer 775 but also in the body region 773.
[212] On the other hand, when the p-type impurity concentration is relatively high near the drain side end (end of the drift layer 775) of the channel region, the concentration of the end of the n-type drift layer 775 decreases. As a result, the ON resistance of the element-side semiconductor device 252 increases.
[213] In the device-side semiconductor device 252, an npn bipolar transistor is formed between the drain electrode 781 and the short circuit electrode 782 by the drain layers 775 and 778, the body region 773, and the source layer 774. Is formed. When a voltage is applied to the bipolar transistor, the depletion layer is extended by d1 longer than the width in the lateral direction of the drift layer 775 as described above.
[214] In the wiring-side semiconductor device 352 shown in FIG. 30, the junction portion 780b and the drift layer 775 form a parasitic diode between the semiconductor substrate 771 and the drain electrode 778. When a voltage is applied to the parasitic diode, the depletion layer is extended by the width d2 of the drift layer 775 in the lateral direction.
[215] Since the width d2 is narrower than the width d1, the withstand voltage of the parasitic diode in the wiring side semiconductor device 352 is lower than that of the bipolar transistor in the element side semiconductor device 252. Therefore, when a large voltage is applied to the semiconductor device during L load switching or the like, the parasitic diode in the wiring-side semiconductor device 352 avalanches breaks down. Therefore, no voltage higher than the breakdown voltage of the parasitic diode is applied to the element-side semiconductor device 252. As a result, the element formed in the semiconductor device according to the present embodiment, that is, the element-side semiconductor device 252 has a large voltage. It is not destroyed.
[216] 31 is an enlarged plan view of a semiconductor device according to the eighth embodiment. The semiconductor device according to the present embodiment differs from the semiconductor device according to the seventh embodiment in that the drain electrode 784 is also formed above the gate wiring 764.
[217] 32 is a cross-sectional view of the wiring-side semiconductor device 354 of the eighth embodiment according to the present invention. As compared with the wiring side semiconductor device 352 shown in FIGS. 28 and 30 in the seventh embodiment, the drain electrode 784 is formed above the gate wiring 764. As a result, since the resistance value of the drain electrode 784 is lowered, the ON resistance of the semiconductor device according to the present embodiment is lower than the ON resistance of the semiconductor device according to the seventh embodiment. In addition, since the element side semiconductor device which concerns on this embodiment is the same structure as the element side semiconductor device in 7th Embodiment, it abbreviate | omits.
[218] 33 is a cross-sectional view of the wiring-side semiconductor device 356 of the ninth embodiment according to the present invention. In this embodiment, the drain electrode 784 is also formed above the gate wiring 764, and the thickness of the wiring insulating film 786 is about the same as that of the gate insulating film 776 of the element-side semiconductor device. It differs from 7th Embodiment in the point.
[219] Since the drain electrode 784 is also formed above the gate wiring 764, the ON resistance of the semiconductor device according to the present embodiment as compared with the ON resistance of the semiconductor device according to the seventh embodiment. Is low. In addition, since the wiring insulating film 786 is approximately equal to the film thickness of the gate insulating film 776, the wiring insulating film 786 of the wiring-side semiconductor device 356 and the gate insulating film 776 of the element-side semiconductor device are in the same process. Can be prepared. In addition, since the element side semiconductor device which concerns on this embodiment is the same structure as the element side semiconductor device in 7th Embodiment, it abbreviate | omits.
[220] 34 is an enlarged plan view of a semiconductor device of a tenth embodiment according to the present invention. According to the seventh embodiment shown in FIG. 28, the source diffusion layer 774 is formed in the shape of a comb teeth, and only the protrusion 774A is in contact with the shorting electrode 782.
[221] However, according to the present embodiment, the source diffusion layer 774 is formed in a long shape on the surface of the semiconductor substrate, and in contact with the short-circuit electrode 782 on one side in the longitudinal direction thereof. As a result, the ON resistance of the semiconductor device according to the present embodiment is lower than the ON resistance of the semiconductor device according to the seventh embodiment. Note that the cross sectional views of the element-side semiconductor device and the wiring-side semiconductor device are the same as those of the semiconductor device according to the seventh embodiment, that is, FIGS.
[222] 35 is an enlarged plan view of a semiconductor device of an eleventh embodiment according to the present invention. Compared with the seventh embodiment shown in FIG. 28, the gate electrode 777a and the gate wiring 764 are different in that they are small. In the seventh embodiment, the gate electrodes 777a and the gate wirings 764 are formed on all the wiring side semiconductor devices (see Fig. 30). However, in this embodiment, the gate electrode 777a and the gate wiring 764 are not formed on the upper side of many wiring-side semiconductor devices. (The gate electrode 777a and the gate wiring 764 are not formed. In addition, in this embodiment, the gate wiring 764 is continuously connected to the bonding pad 762 and the gate connection pattern 763 in the pattern formed with the metal of the same layer. . Therefore, the via 765 like the seventh embodiment is unnecessary.
[223] In addition, similarly to the seventh embodiment, the gate wiring 764 may be formed of the same layer of metal as the shorting electrode 782 or the drain electrode 781, and connected to the gate connection pattern 763 by a via 765. good.
[224] FIG. 36 is an enlarged plan view showing dotted lines S shown in the MOSFET chip shown in FIG. 36 illustrates a portion where the gate electrode 777a and the gate wiring 764 are not formed. The gate electrode 777b extends continuously in a direction substantially perpendicular to the gate wiring 764. The gate electrode 777 is made of a low resistance material such as metal or metal silicide. Also, any gate electrode 777b is connected to the gate wiring 764 and the gate electrode 777a shown in FIG. Although the gate electrode 777a and the gate wiring 764 are not formed on the upper side of many wiring-side semiconductor devices, since the gate electrode 777b is made of a low resistance material, from the gate electrode 777b to the bonding pad 762. The resistance of is low enough. The gate electrodes 777a and the gate wirings 764 may be, for example, only two at the first stage.
[225] On the other hand, a connecting portion 780b (see Fig. 37) is formed under the wiring-side semiconductor device in the same manner as in the seventh embodiment. Thus, the element side semiconductor device can be protected.
[226] FIG. 37 is a cross-sectional view of the wiring-side semiconductor device 358 along line C-C in FIG. The wiring side semiconductor device 358 does not have the gate wiring 764 and the gate electrode 777a. Therefore, there is no need to consider the parasitic capacitance between the gate and the drain. Therefore, like the wiring side semiconductor device 352 shown in FIG. 30, the drain electrode 784 on the connection portion 780 does not need to be removed.
[227] In addition, according to the present embodiment, since the contact between the gate electrode 777a and the connection portion 780b and the parasitic capacitance need not be taken into consideration, the wiring insulating film 786 is unnecessary.
[228] In the present embodiment, when the gate electrode 777 is formed of metal silicide, the short circuit electrode 782 and the drain electrode 781 are also formed of the same metal silicide, whereby the number of electrode layers can be reduced by one.
[229] FIG. 38 is a cross-sectional view of the element-side semiconductor device 260 using the metal plug 782 instead of the connection portion 780 in the element-side semiconductor device 252 shown in FIG. 29. The metal plug 782 reaches the semiconductor substrate 771 from the surface of the epitaxial layer 772.
[230] 39 is a cross-sectional view of the wiring-side semiconductor device 360 using a metal plug 782 instead of the connecting portion 780 in the wiring-side semiconductor device 352 shown in FIG. The metal plug 782 reaches the semiconductor substrate 771 from the surface of the epitaxial layer 772.
[231] As shown in FIG. 38 and FIG. 39, by using the metal plug 782 instead of the connection part 780, the ON resistance of a semiconductor device falls. In addition, since the metal plug can be formed to have a smaller width than the diffusion layer, the semiconductor device can be micronized by using the metal plug.
[232] The element-side semiconductor device 260 may be configured in combination with the wiring-side semiconductor device 360, but may be combined with the wiring-side semiconductor device 352, 354, 356, or 358, for example.
[233] On the other hand, the wiring side semiconductor device 360 may comprise a semiconductor device in combination with the element side semiconductor device 252, for example.
[234] 40 is a schematic partially enlarged plan view of a semiconductor device according to the twelfth embodiment. Compared with the contact-side semiconductor device 300 (see FIG. 3) of the first embodiment, the present embodiment differs in that the source layer 80 is not formed in the contact-side semiconductor device 362. The element side semiconductor device in this embodiment is the same as the element side semiconductor device 200 shown in FIG.
[235] 41 is a cross sectional view of a contact-side semiconductor device 362 in the present embodiment. As in the present embodiment, the same effects as those in the first embodiment can be obtained also by the semiconductor device in which the element-side semiconductor device 200 and the contact-side semiconductor device 362 are combined.
[236] As described above, according to the present invention, it is possible to provide a semiconductor device having a small switching loss due to miniaturization, which can reduce manufacturing costs, prevent device destruction due to L-load switching, and are easy to manufacture. have.

权利要求:
Claims (24)
[1" claim-type="Currently amended] Semiconductor substrate,
A semiconductor surface layer having a higher resistance than the semiconductor substrate and formed on the surface of the semiconductor substrate,
A gate electrode formed on the gate insulating film formed on the surface of the semiconductor surface layer,
A first conductive type drain layer selectively formed on the semiconductor surface layer on one side of the gate electrode,
A drain electrode connected to the drain layer,
A source layer of a first conductive type selectively formed in said semiconductor surface layer on the other side of said gate electrode,
An element side connection portion connected to the source layer and having a lower resistance than the semiconductor surface layer, and selectively formed in the semiconductor surface layer so as not to reach the channel portion between the source layer and the drain layer and the semiconductor substrate in the semiconductor surface layer,
A contact side connection portion selectively lowered in the semiconductor surface layer, having a lower resistance than the semiconductor surface layer, and having a depth greater than that of the device side connection portion,
A first source electrode connecting the source layer, the element side connection portion, and the contact side connection portion;
And a back electrode connected to the semiconductor substrate on the back surface of the semiconductor substrate.
[2" claim-type="Currently amended] The semiconductor device according to claim 1, wherein the back electrode is formed as a second source electrode,
And the contact side connecting portion reaches the semiconductor substrate.
[3" claim-type="Currently amended] The semiconductor device according to claim 2, wherein the element side connection portion and the contact side connection portion are formed of a diffusion layer of a first conductivity type.
[4" claim-type="Currently amended] The semiconductor device according to claim 2, wherein at least one of the element side connection portion and the contact side connection portion is formed of a metal plug.
[5" claim-type="Currently amended] The semiconductor device according to claim 3, wherein one or two or more of said element-side connection portions are formed in a straight line shape,
The contact side connecting portion is formed so as to be adjacent between the element side connecting portion or to overlap the element side connecting portion,
In the cross section perpendicular to the direction of the straight line, the contact side connecting portion is diffused wider or deeper than the element side connecting portion.
[6" claim-type="Currently amended] The semiconductor device according to claim 1, wherein in the element-side semiconductor device in which the element-side connection portion is formed, the drain layer, the channel portion, and the source layer are disposed between the drain electrode and the first source electrode. Thereby forming a first bipolar transistor,
In the contact-side semiconductor device in which the contact-side connection portion is formed, a second bipolar is formed by the drain layer, the channel portion, the contact-side connection portion, and the source layer between the drain electrode and the first source electrode. Transistors are formed,
The breakdown voltage between the drain electrode and the first source electrode in the second bipolar transistor is about equal to or less than the breakdown voltage between the drain electrode and the first source electrode in the first bipolar transistor. A semiconductor device.
[7" claim-type="Currently amended] The semiconductor device according to claim 1, wherein in the element-side semiconductor device in which the element-side connection portion is formed, the drain layer, the channel portion, and the source layer are disposed between the drain electrode and the first source electrode. Thereby forming a bipolar transistor,
In the contact-side semiconductor device where the contact-side connection portion is formed, a diode is formed by the drain layer and the channel portion without the source layer between the drain electrode and the first source electrode.
And the breakdown voltage between the drain electrode and the first source electrode in the diode is about equal to or less than the breakdown voltage between the drain electrode and the first source electrode in the bipolar transistor.
[8" claim-type="Currently amended] The semiconductor device according to claim 6, wherein the drain layer includes a high concentration layer having a relatively low resistance, and a field resistance portion having a relatively high resistance formed around the high concentration layer.
The width of the field relaxing portion in the direction of the channel portion from the high concentration layer in the contact side semiconductor device is smaller than the width of the field relaxing portion in the direction of the channel portion from the high concentration layer in the element side semiconductor device. A semiconductor device.
[9" claim-type="Currently amended] The semiconductor device according to claim 7, wherein the drain layer comprises a high concentration layer having a relatively low resistance and a relatively high field relaxation portion formed around the high concentration layer.
The width of the field relaxing portion in the direction of the channel portion from the high concentration layer in the contact side semiconductor device is smaller than the width of the field relaxing portion in the direction of the channel portion from the high concentration layer in the element side semiconductor device. A semiconductor device.
[10" claim-type="Currently amended] The semiconductor device according to claim 1, wherein the gate electrode is formed in the element side semiconductor device, but is not formed in the contact side semiconductor device.
[11" claim-type="Currently amended] The semiconductor device according to claim 1, wherein the semiconductor substrate is of a second conductivity type,
The back electrode is the drain electrode,
A metal plug penetrating the semiconductor surface layer from the drain layer to the semiconductor substrate to connect the drain layer and the semiconductor substrate;
And the first source electrode is connected to a surface of the semiconductor substrate.
[12" claim-type="Currently amended] A semiconductor device according to claim 1, wherein a plurality of device units each comprising the gate electrode, the drain layer, the source layer, the element side connection portion, the contact side connection portion, the source electrode and the drain electrode are formed; And the device units adjacent to each other share either the source electrode or the drain electrode.
[13" claim-type="Currently amended] 13. The semiconductor device according to claim 12, wherein the element unit includes a connection string in which a plurality of the element side connection portions and the plurality of contact side connection portions are alternately adjacently arranged in a straight line, and a drain string in which the drain layer is arranged in a linear shape. Equipped with
The rows of connections adjacent to each other are nearly parallel,
And the drain row is substantially parallel to the connection row between the connection rows adjacent to each other.
[14" claim-type="Currently amended] A semiconductor device according to claim 12, wherein in the device unit,
1 or 2 or more element side connection parts are formed in a straight line shape,
The drain layer is formed in a direction parallel to the direction of the straight line of the element-side connection portion,
And said contact side connecting portion extends in a direction perpendicular to said linear direction, is in contact with said element side connecting portion, and is formed in the vicinity of said drain layer.
[15" claim-type="Currently amended] The semiconductor device according to claim 1, wherein the element side connection portion and the contact side connection portion are integrally formed.
[16" claim-type="Currently amended] The semiconductor device according to claim 1, wherein in the device side semiconductor device in which the element side connection portion is formed, the drain layer, the channel portion, and the source layer are disposed between the drain electrode and the first source electrode. Thereby forming a bipolar transistor,
In the contact-side semiconductor device in which the contact-side connection part is formed, the drain layer and the contact-side connection part or the second conductive type adjacent thereto without the source layer between the drain electrode and the first source electrode. The diode is formed by the semiconductor region of
And the breakdown voltage between the drain electrode and the first source electrode in the diode is about equal to or less than the breakdown voltage between the drain electrode and the first source electrode in the bipolar transistor.
[17" claim-type="Currently amended] Semiconductor substrate,
A semiconductor surface layer having a higher resistance than the semiconductor substrate and formed on the surface of the semiconductor substrate,
A gate electrode formed on the gate insulating film formed on the surface of the semiconductor surface layer,
A first conductive type drain layer selectively formed on the semiconductor surface layer on one side of the gate electrode,
A drain electrode connected to the drain layer,
A source layer of a first conductive type selectively formed in said semiconductor surface layer on the other side of said gate electrode,
A first semiconductor region of a second conductivity type connected to said source layer, having a lower resistance than said semiconductor surface layer, and selectively formed in said semiconductor surface layer to reach said semiconductor substrate,
A second semiconductor region of a second conductivity type having a lower resistance than the semiconductor surface layer, and selectively formed in the semiconductor surface layer to reach the semiconductor substrate, wherein the source layer is not adjacent to the semiconductor layer;
A short electrode connected to the source layer and the first semiconductor region,
A source electrode connected to the semiconductor substrate on the back surface of the semiconductor substrate,
A bipolar transistor provided between the drain electrode and the short circuit electrode and formed by the drain layer, the source layer, and a channel portion between the drain layer and the source layer;
A diode provided between the drain electrode and the second semiconductor region, the diode formed by the drain layer and the second semiconductor region;
And the breakdown voltage between the drain layer and the second semiconductor region in the diode is approximately equal to or less than the breakdown voltage between the drain electrode and the source layer in the bipolar transistor.
[18" claim-type="Currently amended] 18. The semiconductor device according to claim 17, wherein the first semiconductor region extends along the source layer,
And the second semiconductor region extends substantially perpendicular to the first semiconductor region.
[19" claim-type="Currently amended] 19. The semiconductor device according to claim 18, wherein the second semiconductor region extends along the gate wiring below the gate wiring connected to the gate electrode.
[20" claim-type="Currently amended] The semiconductor device according to claim 19, wherein a wiring insulating film thicker than the gate insulating film is interposed between the gate electrode and the gate wiring and the second semiconductor region.
[21" claim-type="Currently amended] The semiconductor device according to claim 19, wherein the drain electrode does not exist above the gate wiring.
[22" claim-type="Currently amended] The semiconductor device according to claim 17, wherein the source layer is formed in a comb-tooth shaped shape having a protrusion in the plane of the semiconductor substrate,
The projecting portion is connected to the short circuit electrode.
[23" claim-type="Currently amended] 18. The semiconductor device according to claim 17, wherein any one or all of the drain layer, the source layer, the gate electrode, the drain electrode, the source electrode, or the shorting electrode is formed on a plane of the semiconductor substrate. A semiconductor device characterized by being round in shape.
[24" claim-type="Currently amended] The semiconductor device according to claim 17, wherein the first semiconductor region and the second semiconductor region are formed simultaneously in the same process.

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US5592005A|1997-01-07|Punch-through field effect transistor

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JP4534303B2|2010-09-01|Horizontal super junction semiconductor device

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同族专利:

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公开号 | 公开日

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JP2003031805A|2003-01-31|

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US7067876B2|2006-06-27|

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KR100531924B1|2005-11-28|

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CN1416178A|2003-05-07|

---

EP1256985A2|2002-11-13|

---

EP1256985B1|2012-04-25|

---

US20020167047A1|2002-11-14|

---

EP1256985A3|2009-12-16|

---

CN1262019C|2006-06-28|

---

JP4070485B2|2008-04-02|

引用文献:

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公开号 | 申请日 | 公开日 | 申请人 | 专利标题

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法律状态:
2001-05-09|Priority to JPJP-P-2001-00139060

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2001-05-09|Priority to JP2001139060

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2002-03-07|Priority to JP2002061988A

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2002-03-07|Priority to JPJP-P-2002-00061988

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2002-05-08|Application filed by 가부시끼가이샤 도시바

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2002-11-16|Publication of KR20020085850A

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2005-11-28|Application granted

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2005-11-28|Publication of KR100531924B1

优先权:

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申请号 | 申请日 | 专利标题

---

JPJP-P-2001-00139060|2001-05-09|

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JP2001139060|2001-05-09|

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JP2002061988A|JP4070485B2|2001-05-09|2002-03-07|Semiconductor device|

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JPJP-P-2002-00061988|2002-03-07|